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C8051F380/1/2/3/4/5/6/7/C
USB Register Definition 21.22. EOUTCSRL: USB0 OUT Endpoint Control Low Byte
Bit
Name
Type
Reset
7
CLRDT
W
0
6
STSTL
R/W
0
5
SDSTL
R/W
0
4
FLUSH
R/W
0
3
DATERR
R
0
2
OVRUN
R/W
0
1
FIFOFUL
R
0
0
OPRDY
R/W
0
USB Register Address = 0x14
Bit Name Description
Write
Read
7
CLRDT
Clear Data Toggle Bit. Software should write 1 to
This bit always reads 0.
this bit to reset the OUT end-
point data toggle to 0.
6
5
4
STSTL
SDSTL
FLUSH
Sent Stall Bit.
Hardware sets this bit to 1 when a STALL handshake signal is transmitted. This flag
must be cleared by software.
Send Stall Bit.
Software should write 1 to this bit to generate a STALL handshake. Software should
write 0 to this bit to terminate the STALL signal. This bit has no effect in ISO mode.
FIFO Flush Bit.
Writing a 1 to this bit flushes the next packet to be read from the OUT endpoint FIFO.
The FIFO pointer is reset and the OPRDY bit is cleared. Multiple packets must be
flushed individually. Hardware resets the FLUSH bit to 0 when the flush is complete.
Note: If data for the current packet has already been read from the FIFO, the FLUSH bit should
not be used to flush the packet. Instead, the FIFO should be read manually.
3
2
1
DATERR Data Error Bit.
In ISO mode, this bit is set by hardware if a received packet has a CRC or bit-stuffing
error. It is cleared when software clears OPRDY. This bit is only valid in ISO mode.
OVRUN Data Overrun Bit.
This bit is set by hardware when an incoming data packet cannot be loaded into the
OUT endpoint FIFO. This bit is only valid in ISO mode, and must be cleared by software.
0: No data overrun.
1: A data packet was lost because of a full FIFO since this flag was last cleared.
FIFOFUL OUT FIFO Full.
This bit indicates the contents of the OUT FIFO. If double buffering is enabled (DBIEN =
1), the FIFO is full when the FIFO contains two packets. If DBIEN = 0, the FIFO is full
when the FIFO contains one packet.
0: OUT endpoint FIFO is not full.
1: OUT endpoint FIFO is full.
0
202
OPRDY
OUT Packet Ready.
Hardware sets this bit to 1 and generates an interrupt when a data packet is available.
Software should clear this bit after each data packet is unloaded from the OUT endpoint
FIFO.
Rev. 1.4
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